Page 1
CYGNAL Integrated Products, Inc.
2002
4.2002; Rev. 1.4
Mixed-Signal 32KB ISP FLASH MCU Family
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
JTAG
32KB
ISP FLASH
256/2304 B
SRAM
SANITY
CONTROL
+
-
SAR
ADC
CLOCK
CIRCUIT
PGA
VREF
12-Bit
DAC
AMUX
TEMP
SENSOR
VOLTAGE
COMPARATORS
ANALOG PERIPHERALS
Port 0
Port 1
UART
SMBus
SPI Bus
PCA
Po
rt
2
Port 3
CROSS
BAR
Timer 0
Timer 1
Timer 2
Timer 3
DIGITAL I/O
HIGH-SPEED CONTROLLER CORE
DEBUG
CIRCUITRY
21
INTERRUPTS
8051 CPU
(25MIPS)
12-Bit
DAC
+
-
ANALOG PERIPHERALS
-
SAR ADC
12-Bit (C8051F000/1/2, C8051F005/6/7)
10-bit (C8051F010/1/2, C8051F015/6/7)
1LSB INL; No Missing Codes
Programmable Throughput up to 100ksps
Up to 8 External Inputs; Programmable as Single-
Ended or Differential
Programmable Amplifier Gain: 16, 8, 4, 2, 1, 0.5
Data Dependent Windowed Interrupt Generator
Built-in Temperature Sensor (
3C)
-
Two 12-bit DACs
-
Two Analog Comparators
Programmable Hysteresis Values
Configurable to Generate Interrupts or Reset
-
Voltage Reference
2.4V; 15 ppm/
C
Available on External Pin
-
Precision VDD Monitor/Brown-out Detector
ON-CHIP JTAG DEBUG & BOUNDRY SCAN
-
On-Chip Debug Circuitry Facilitates Full Speed, Non-
Intrusive In-System Debug (No Emulator Required!)
-
Provides Breakpoints, Single Stepping, Watchpoints, Stack
Monitor
-
Inspect/Modify Memory and Registers
-
Superior Performance to Emulation Systems Using ICE-
Chips, Target Pods, and Sockets
-
IEEE1149.1 Compliant Boundary Scan
-
Low Cost Development Kit
HIGH SPEED 8051
C CORE
-
Pipelined Instruction Architecture; Executes 70% of
Instruction Set in 1 or 2 System Clocks
-
Up to 25MIPS Throughput with 25MHz Clock
-
21 Vectored Interrupt Sources
MEMORY
-
256 Bytes Internal Data RAM (F000/01/02/10/11/12)
-
2304 Bytes Internal Data RAM (F005/06/07/15/16/17)
-
32k Bytes FLASH; In-System Programmable in 512 byte
Sectors
DIGITAL PERIPHERALS
-
4 Byte-Wide Port I/O; All are 5V tolerant
-
Hardware SMBus
TM
(I2C
TM
Compatible), SPI
TM
, and UART
Serial Ports Available Concurrently
-
Programmable 16-bit Counter/Timer Array with Five
Capture/Compare Modules
-
Four General Purpose 16-bit Counter/Timers
-
Dedicated Watch-Dog Timer
-
Bi-directional Reset
CLOCK SOURCES
-
Internal Programmable Oscillator: 2-to-16MHz
-
External Oscillator: Crystal, RC,C, or Clock
-
Can Switch Between Clock Sources on-the-fly; Useful in
Power Saving Modes
SUPPLY VOLTAGE ........................ 2.7V to 3.6V
-
Typical Operating Current: 12.5mA @ 25MHz
-
Multiple Power Saving Sleep and Shutdown Modes
64-Pin TQFP, 48-Pin TQFP, 32-Pin LQFP
Temperature Range: 40
C to +85C
Page 2
CYGNAL Integrated Products, Inc.
2002
4.2002; Rev. 1.4
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
TABLE OF CONTENTS
1. SYSTEM OVERVIEW ....................................................................................................... 8
Table 1.1. Product Selection Guide................................................................................................................... 8
Figure 1.1. C8051F000/05/10/15 Block Diagram............................................................................................. 9
Figure 1.2. C8051F001/06/11/16 Block Diagram........................................................................................... 10
Figure 1.3. C8051F002/07/12/17 Block Diagram........................................................................................... 11
1.1.
CIP-51
TM
CPU ...................................................................................................................................... 12
Figure 1.4. Comparison of Peak MCU Execution Speeds............................................................................... 12
Figure 1.5. On-Board Clock and Reset ........................................................................................................... 13
1.2.
On-Board Memory ................................................................................................................................ 14
Figure 1.6. On-Board Memory Map ............................................................................................................... 14
1.3.
JTAG Debug and Boundary Scan ......................................................................................................... 15
Figure 1.7. Debug Environment Diagram ....................................................................................................... 15
1.4.
Programmable Digital I/O and Crossbar ............................................................................................... 16
Figure 1.8. Digital Crossbar Diagram ............................................................................................................. 16
1.5.
Programmable Counter Array ............................................................................................................... 17
Figure 1.9. PCA Block Diagram ..................................................................................................................... 17
1.6.
Serial Ports ............................................................................................................................................ 17
1.7.
Analog to Digital Converter .................................................................................................................. 18
Figure 1.10. ADC Diagram ............................................................................................................................. 18
1.8.
Comparators and DACs......................................................................................................................... 19
Figure 1.11. Comparator and DAC Diagram .................................................................................................. 19
2. ABSOLUTE MAXIMUM RATINGS*............................................................................ 20
3. GLOBAL DC ELECTRICAL CHARACTERISTICS .................................................. 20
4. PINOUT AND PACKAGE DEFINITIONS.................................................................... 21
Table 4.1. Pin Definitions ............................................................................................................................... 21
Figure 4.1. TQFP-64 Pinout Diagram............................................................................................................. 23
Figure 4.2. TQFP-64 Package Drawing .......................................................................................................... 24
Figure 4.3. TQFP-48 Pinout Diagram............................................................................................................. 25
Figure 4.4. TQFP-48 Package Drawing .......................................................................................................... 26
Figure 4.5. LQFP-32 Pinout Diagram ............................................................................................................. 27
Figure 4.6. LQFP-32 Package Drawing .......................................................................................................... 28
5. ADC (12-Bit, C8051F000/1/2/5/6/7 Only) ........................................................................ 29
Figure 5.1. 12-Bit ADC Functional Block Diagram........................................................................................ 29
5.1.
Analog Multiplexer and PGA................................................................................................................ 29
5.2.
ADC Modes of Operation ..................................................................................................................... 30
Figure 5.2. 12-Bit ADC Track and Conversion Example Timing................................................................... 30
Figure 5.3. Temperature Sensor Transfer Function......................................................................................... 31
Figure 5.4. AMX0CF: AMUX Configuration Register (C8051F00x) ............................................................ 31
Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F00x)........................................................... 32
Figure 5.6. ADC0CF: ADC Configuration Register (C8051F00x) ................................................................. 33
Figure 5.7. ADC0CN: ADC Control Register (C8051F00x) .......................................................................... 34
Figure 5.8. ADC0H: ADC Data Word MSB Register (C8051F00x) ............................................................. 35
Figure 5.9. ADC0L: ADC Data Word LSB Register (C8051F00x)............................................................... 35
5.3.
ADC Programmable Window Detector................................................................................................. 36
Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F00x)................................... 36
Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F00x).................................... 36
Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F00x)........................................ 36
Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F00x) ......................................... 36
Figure 5.14. 12-Bit ADC Window Interrupt Examples, Right Justified Data ................................................. 37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 37
Figure 5.15. 12-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 38
4.2002; Rev. 1.4
CYGNAL Integrated Products, Inc.
2002
Page
3
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 5.1. 12-Bit ADC Electrical Characteristics ........................................................................................... 38
Table 5.1. 12-Bit ADC Electrical Characteristics ........................................................................................... 39
6. ADC (10-Bit, C8051F010/1/2/5/6/7 Only) ........................................................................ 40
Figure 6.1. 10-Bit ADC Functional Block Diagram........................................................................................ 40
6.1.
Analog Multiplexer and PGA................................................................................................................ 40
6.2.
ADC Modes of Operation ..................................................................................................................... 41
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing................................................................... 41
Figure 6.3. Temperature Sensor Transfer Function......................................................................................... 42
Figure 6.4. AMX0CF: AMUX Configuration Register (C8051F01x) ............................................................ 42
Figure 6.5. AMX0SL: AMUX Channel Select Register (C8051F01x)........................................................... 43
Figure 6.6. ADC0CF: ADC Configuration Register (C8051F01x) ................................................................. 44
Figure 6.7. ADC0CN: ADC Control Register (C8051F01x) .......................................................................... 45
Figure 6.8. ADC0H: ADC Data Word MSB Register (C8051F01x) ............................................................. 46
Figure 6.9. ADC0L: ADC Data Word LSB Register (C8051F01x)............................................................... 46
6.3.
ADC Programmable Window Detector................................................................................................. 47
Figure 6.10. ADC0GTH: ADC Greater-Than Data High Byte Register (C8051F01x)................................... 47
Figure 6.11. ADC0GTL: ADC Greater-Than Data Low Byte Register (C8051F01x).................................... 47
Figure 6.12. ADC0LTH: ADC Less-Than Data High Byte Register (C8051F01x)........................................ 47
Figure 6.13. ADC0LTL: ADC Less-Than Data Low Byte Register (C8051F01x) ......................................... 47
Figure 6.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data ................................................. 48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 48
Figure 6.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ................................................... 49
Table 6.1. 10-Bit ADC Electrical Characteristics ........................................................................................... 49
Table 6.1. 10-Bit ADC Electrical Characteristics ........................................................................................... 50
7. DACs, 12 BIT VOLTAGE MODE................................................................................... 51
Figure 7.1. DAC Functional Block Diagram.................................................................................................... 51
Figure 7.2. DAC0H: DAC0 High Byte Register ............................................................................................. 52
Figure 7.3. DAC0L: DAC0 Low Byte Register .............................................................................................. 52
Figure 7.4. DAC0CN: DAC0 Control Register............................................................................................... 52
Figure 7.5. DAC1H: DAC1 High Byte Register ............................................................................................. 53
Figure 7.6. DAC1L: DAC1 Low Byte Register .............................................................................................. 53
Figure 7.7. DAC1CN: DAC1 Control Register............................................................................................... 53
Table 7.1. DAC Electrical Characteristics ...................................................................................................... 54
8. COMPARATORS.............................................................................................................. 55
Figure 8.1. Comparator Functional Block Diagram ........................................................................................ 55
Figure 8.2. Comparator Hysteresis Plot .......................................................................................................... 56
Figure 8.3. CPT0CN: Comparator 0 Control Register .................................................................................... 57
Figure 8.4. CPT1CN: Comparator 1 Control Register .................................................................................... 58
Table 8.1. Comparator Electrical Characteristics............................................................................................ 59
9. VOLTAGE REFERENCE................................................................................................ 60
Figure 9.1. Voltage Reference Functional Block Diagram ............................................................................. 60
Figure 9.2. REF0CN: Reference Control Register .......................................................................................... 61
Table 9.1. Reference Electrical Characteristics............................................................................................... 61
10. CIP-51 CPU ........................................................................................................................ 62
Figure 10.1. CIP-51 Block Diagram ............................................................................................................... 62
10.1.
INSTRUCTION SET ........................................................................................................................ 63
Table 10.1. CIP-51 Instruction Set Summary.................................................................................................. 64
10.2.
MEMORY ORGANIZATION.......................................................................................................... 67
Figure 10.2. Memory Map .............................................................................................................................. 68
10.3.
SPECIAL FUNCTION REGISTERS ............................................................................................... 69
Table 10.2. Special Function Register Memory Map...................................................................................... 69
Table 10.3. Special Function Registers........................................................................................................... 69
Figure 10.3. SP: Stack Pointer ........................................................................................................................ 73
Figure 10.4. DPL: Data Pointer Low Byte ...................................................................................................... 73
Page 4
CYGNAL Integrated Products, Inc.
2002
4.2002; Rev. 1.4
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 10.5. DPH: Data Pointer High Byte..................................................................................................... 73
Figure 10.6. PSW: Program Status Word ....................................................................................................... 74
Figure 10.7. ACC: Accumulator ..................................................................................................................... 75
Figure 10.8. B: B Register............................................................................................................................... 75
10.4.
INTERRUPT HANDLER................................................................................................................. 76
Table 10.4. Interrupt Summary ....................................................................................................................... 77
Figure 10.9. IE: Interrupt Enable .................................................................................................................... 78
Figure 10.10. IP: Interrupt Priority ................................................................................................................. 79
Figure 10.11. EIE1: Extended Interrupt Enable 1 ........................................................................................... 80
Figure 10.12. EIE2: Extended Interrupt Enable 2 ........................................................................................... 81
Figure 10.13. EIP1: Extended Interrupt Priority 1 .......................................................................................... 82
Figure 10.14. EIP2: Extended Interrupt Priority 2 .......................................................................................... 83
10.5.
Power Management Modes ............................................................................................................... 84
Figure 10.15. PCON: Power Control Register ................................................................................................ 85
11. FLASH MEMORY............................................................................................................ 86
11.1.
Programming The Flash Memory...................................................................................................... 86
Table 11.1. FLASH Memory Electrical Characteristics.................................................................................. 86
11.2.
Non-volatile Data Storage ................................................................................................................. 87
11.3.
Security Options................................................................................................................................ 87
Figure 11.1. PSCTL: Program Store RW Control........................................................................................... 87
Figure 11.2. Flash Program Memory Security Bytes ....................................................................................... 88
Figure 11.3. FLACL: Flash Access Limit (C8051F005/06/07/15/16/17 only) ............................................... 89
Figure 11.4. FLSCL: Flash Memory Timing Prescaler ................................................................................... 90
12. EXTERNAL RAM (C8051F005/06/07/15/16/17) ............................................................ 91
Figure 12.1. EMI0CN: External Memory Interface Control ........................................................................... 91
13. RESET SOURCES ............................................................................................................ 92
Figure 13.1. Reset Sources Diagram ............................................................................................................... 92
13.1.
Power-on Reset ................................................................................................................................. 93
13.2.
Software Forced Reset....................................................................................................................... 93
Figure 13.2. VDD Monitor Timing Diagram .................................................................................................. 93
13.3.
Power-fail Reset ................................................................................................................................ 93
13.4.
External Reset ................................................................................................................................... 94
13.5.
Missing Clock Detector Reset ........................................................................................................... 94
13.6.
Comparator 0 Reset........................................................................................................................... 94
13.7.
External CNVSTR Pin Reset ............................................................................................................ 94
13.8.
Watchdog Timer Reset...................................................................................................................... 94
Figure 13.3. WDTCN: Watchdog Timer Control Register ............................................................................. 95
Figure 13.4. RSTSRC: Reset Source Register ................................................................................................ 96
Table 13.1. Reset Electrical Characteristics.................................................................................................... 97
14. OSCILLATOR................................................................................................................... 98
Figure 14.1. Oscillator Diagram...................................................................................................................... 98
Figure 14.2. OSCICN: Internal Oscillator Control Register ........................................................................... 99
Table 14.1. Internal Oscillator Electrical Characteristics................................................................................ 99
Figure 14.3. OSCXCN: External Oscillator Control Register....................................................................... 100
14.1.
External Crystal Example................................................................................................................ 101
14.2.
External RC Example...................................................................................................................... 101
14.3.
External Capacitor Example............................................................................................................ 101
15. PORT INPUT/OUTPUT ................................................................................................. 102
15.1.
Priority Cross Bar Decoder ............................................................................................................. 102
15.2.
Port I/O Initialization ...................................................................................................................... 102
Figure 15.1. Port I/O Functional Block Diagram .......................................................................................... 103
Figure 15.2. Port I/O Cell Block Diagram .................................................................................................... 103
Table 15.1. Crossbar Priority Decode........................................................................................................... 104
Figure 15.3. XBR0: Port I/O CrossBar Register 0 ........................................................................................ 105
4.2002; Rev. 1.4
CYGNAL Integrated Products, Inc.
2002
Page
5
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Figure 15.4. XBR1: Port I/O CrossBar Register 1 ........................................................................................ 106
Figure 15.5. XBR2: Port I/O CrossBar Register 2 ........................................................................................ 107
15.3.
General Purpose Port I/O ................................................................................................................ 108
15.4.
Configuring Ports Which are not Pinned Out.................................................................................. 108
Figure 15.6. P0: Port0 Register ..................................................................................................................... 108
Figure 15.7. PRT0CF: Port0 Configuration Register .................................................................................... 108
Figure 15.8. P1: Port1 Register ..................................................................................................................... 109
Figure 15.9. PRT1CF: Port1 Configuration Register .................................................................................... 109
Figure 15.10. PRT1IF: Port1 Interrupt Flag Register ................................................................................... 109
Figure 15.11. P2: Port2 Register ................................................................................................................... 110
Figure 15.12. PRT2CF: Port2 Configuration Register .................................................................................. 110
Figure 15.13. P3: Port3 Register ................................................................................................................... 111
Figure 15.14. PRT3CF: Port3 Configuration Register .................................................................................. 111
Table 15.2. Port I/O DC Electrical Characteristics ....................................................................................... 111
16. SMBus / I2C Bus.............................................................................................................. 112
Figure 16.1. SMBus Block Diagram............................................................................................................. 112
Figure 16.2. Typical SMBus Configuration .................................................................................................. 113
16.1.
Supporting Documents .................................................................................................................... 113
16.2.
Operation......................................................................................................................................... 114
Figure 16.3. SMBus Transaction................................................................................................................... 114
16.3.
Arbitration....................................................................................................................................... 115
16.4.
Clock Low Extension ...................................................................................................................... 115
16.5.
Timeouts.......................................................................................................................................... 115
16.6.
SMBus Special Function Registers ................................................................................................. 115
Figure 16.4. SMB0CN: SMBus Control Register .......................................................................................... 117
Figure 16.5. SMB0CR: SMBus Clock Rate Register.................................................................................... 118
Figure 16.6. SMB0DAT: SMBus Data Register ........................................................................................... 119
Figure 16.7. SMB0ADR: SMBus Address Register ..................................................................................... 119
Figure 16.8. SMB0STA: SMBus Status Register.......................................................................................... 120
Table 16.1. SMBus Status Codes.................................................................................................................. 121
17. SERIAL PERIPHERAL INTERFACE BUS................................................................ 122
Figure 17.1. SPI Block Diagram ................................................................................................................... 122
Figure 17.2. Typical SPI Interconnection ..................................................................................................... 123
17.1.
Signal Descriptions ......................................................................................................................... 123
17.2.
Operation......................................................................................................................................... 124
Figure 17.3. Full Duplex Operation .............................................................................................................. 124
17.3.
Serial Clock Timing ........................................................................................................................ 125
Figure 17.4. Data/Clock Timing Diagram..................................................................................................... 125
17.4.
SPI Special Function Registers ....................................................................................................... 126
Figure 17.5. SPI0CFG: SPI Configuration Register...................................................................................... 126
Figure 17.6. SPI0CN: SPI Control Register.................................................................................................. 127
Figure 17.7. SPI0CKR: SPI Clock Rate Register.......................................................................................... 128
Figure 17.8. SPI0DAT: SPI Data Register.................................................................................................... 128
18. UART ................................................................................................................................ 129
Figure 18.1. UART Block Diagram .............................................................................................................. 129
18.1.
UART Operational Modes .............................................................................................................. 130
Table 18.1. UART Modes............................................................................................................................. 130
Figure 18.2. UART Mode 0 Interconnect ..................................................................................................... 130
Figure 18.3. UART Mode 0 Timing Diagram............................................................................................... 130
Figure 18.4. UART Mode 1 Timing Diagram............................................................................................... 131
Figure 18.5. UART Modes 1, 2, and 3 Interconnect Diagram ...................................................................... 132
Figure 18.6. UART Modes 2 and 3 Timing Diagram ................................................................................... 132
18.2.
Multiprocessor Communications..................................................................................................... 133
Figure 18.7. UART Multi-Processor Mode Interconnect Diagram............................................................... 133
PDF 
ZIP